1. Field of the Invention
The present invention relates to a printed circuit board (PCB) having a bump interconnection structure, and more particularly to a printed circuit board having a reliable bump interconnection structure, a method of fabricating the same, and a semiconductor package using the same.
2. Description of the Related Art
Generally, respective layers of a multi-layered printed circuit board are interconnected by mechanically processes to form holes in and plate the printed circuit board. These conventional interconnection methods, however, cannot decrease the area of the printed circuit board, perform fine mountings, obtain freedom of design, nor obtain low electrical resistance. In order to address these problems, a bump interconnection structure, i.e., Neo Manhattan Bump Interconnection (NMBI), has been suggested.
FIGS. 1 through 4 are sectional views illustrating a method of fabricating a conventional printed circuit board having an NMBI structure. FIGS. 5 and 6 are partially enlarged sectional views illustrating a hot pressing process (method) of FIG. 3 in more detail.
Referring to FIGS. 1 and 2, copper bumps 12 are formed on a first interconnection layer 10 composed of a copper rail by electro-plating. Then, a resin layer 14, such as a polyimide layer is laminated on the copper bumps 12.
Referring to FIGS. 3, 5, and 6, a second interconnection layer 16, such as a copper foil is disposed on the copper bumps 12 and the resin layer 14. The first interconnection layer 10 is interconnected to the second interconnection layer 16 by the copper bumps 12. That is, the second interconnection layer 16 and the first interconnection layer 10 are pressed as denoted by the arrows in FIG. 6 to reduce the volume of the copper bumps 12 by hot pressing; thereby bonding the second interconnection layer 16 and the copper bumps 12.
Referring to FIG. 4, the first interconnection layer 10 and the second interconnection layer 16 are patterned as required, thereby forming first interconnection layer patterns 10a and second interconnection layer patterns 16a. In this manner, the first interconnection layer patterns 10a and the second interconnection layer patterns 16a are interconnected via the copper bumps 12.
However, as illustrated in FIGS. 4 and 6, a crack may occur in the hot pressed portion 18 of the conventional printed circuit board when the second interconnection layer 16 is hot pressed to the copper bumps 12. When the printed circuit board involving the crack is subjected to reliability tests, such as a temperature cycle test and a dropping test, the hot pressed portion 18 may become separated. That is, the second interconnection layer pattern 16a may separate from the copper bump 12. Therefore, the reliability of the conventional printed circuit board may be substantially degraded due to this potentially problematic hot pressed portion 18.
Similarly, when a semiconductor package, in which a semiconductor chip (not shown) is interconnected to the first interconnection pattern 10a of the printed circuit board, is subjected to reliability tests, such as the temperature cycle test and the dropping test, the hot pressed portion 18 may be separated; thereby degrading the semiconductor package.